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1 2 megabit (256k x 8) multi-purpose flash SST39SF020 preliminary specifications 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ? 1998 silicon storage technology, inc. the sst logo and superflash are registered trademarks of silicon storage technology, inc . mpf is a trademark of silicon storage technology, inc. 326-10 12/98 these specifications are subject to change without notice. features: ? organized as 256 k x 8 ? single 5.0v read and write operations ? superior reliability C endurance: 100,000 cycles (typical) C greater than 100 years data retention ? low power consumption: C active current: 20 ma (typical) C standby current: 10 a (typical) ? sector erase capability C uniform 4 kbyte sectors ? fast read access time: C 70 and 90 ns ? latched address and data ? fast sector erase and byte program: C sector erase time: 7 ms (typical) C chip erase time: 15 ms (typical) C byte program time: 20 s (typical) C chip rewrite time: 5 seconds (typical) ? automatic write timing - internal v pp generation ? end of write detection C toggle bit C data# polling ? ttl i/o compatibility ? jedec standard C eeprom pinouts and command set ? packages available C 32-pin pdip C 32-pin plcc C 32-pin tsop (8mm x 14mm) product description the SST39SF020 is a 256k x 8 cmos multi-purpose flash (mpf) manufactured with ssts proprietary, high performance cmos superflash technology. the split gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the SST39SF020 device writes (program or erase) with a 5.0v-only power supply. the SST39SF020 device conforms to jedec standard pinouts for x8 memories. featuring high performance byte program, the SST39SF020 device provides a maximum byte-pro- gram time of 30 sec. the entire memory can be erased and programmed byte by byte typically in 5 seconds, when using interface features such as toggle bit or data# polling to indicate the completion of program operation. to protect against inadvertent write, the SST39SF020 device has on-chip hardware and soft- ware data protection schemes. designed, manufac- tured, and tested for a wide spectrum of applications, the SST39SF020 device is offered with a guaranteed endur- ance of 10,000 cycles. data retention is rated at greater than 100 years. the SST39SF020 device is suited for applications that require convenient and economical updating of program, configuration, or data memory. for all system applica- tions, the SST39SF020 device significantly improves performance and reliability, while lowering power consumption. the SST39SF020 inherently uses less energy during erase and program than alternative flash technologies. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash tech- nology uses less current to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash tech- nologies. the SST39SF020 device also improves flex- ibility while lowering the cost for program, data, and configuration storage applications. the superflash technology provides fixed erase and program times, independent of the number of endurance cycles that have occurred. therefore the system soft- ware or hardware does not have to be modified or de- rated as is necessary with alternative flash technologies, whose erase and program times increase with accumu- lated endurance cycles. to meet high density, surface mount requirements, the SST39SF020 device is offered in 32-pin tsop and 32- pin plcc packages. a 600 mil, 32-pin pdip is also available. see figures 1 and 2 for pinouts. device operation commands are used to initiate the memory operation functions of the device. commands are written to the device using standard microprocessor write sequences. a command is written by asserting we# low while
2 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications keeping ce# low. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. read the read operation of the SST39SF020 device is con- trolled by ce# and oe#, both have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is dese- lected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to the read cycle timing diagram for further details (figure 3). byte program operation the SST39SF020 device is programmed on a byte-by- byte basis. the program operation consists of three steps. the first step is the three-byte-load sequence for software data protection. the second step is to load byte address and byte data. during the byte program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, which- ever occurs first. the third step is the internal program operation which is initiated after the rising edge of the fourth we# or ce#, whichever occurs first. the program operation, once initiated, will be completed, within 30 s. see figures 4 and 5 for we# and ce# controlled program operation timing diagrams and figure 14 for flowcharts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. any commands written during the inter- nal program operation will be ignored. sector erase operation the sector erase operation allows the system to erase the device on a sector by sector basis. the sector architecture is based on uniform sector size of 4 kbyte. the sector erase operation is initiated by executing a six-byte-command load sequence for software data pro- tection with sector erase command (30h) and sector address (sa) in the last bus cycle. the address lines a12-a17 will be used to determine the sector address. the sector address is latched on the falling edge of the sixth we# pulse , while the command (30h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end of erase can be determined using either data# polling or toggle bit methods. see figure 8 for timing waveforms. any commands written during the sector erase opera- tion will be ignored. chip-erase operation the SST39SF020 device provides a chip-erase opera- tion, which allows the user to erase the entire memory array to the 1s state. this is useful when the entire device must be quickly erased. the chip erase operation is initiated by executing a six- byte software data protection command sequence with chip erase command (10h) with address 5555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. see table 4 for the command sequence, figure 9 for timing diagram, and figure 17 for the flowchart. any commands written during the chip erase operation will be ignored. write operation status detection the SST39SF020 device provides two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the software detection includes two status bits : data# polling (dq 7 ) and toggle bit (dq 6 ). the end of write detection mode is enabled after the rising edge of we# which initiates the internal program or erase cycle. the actual completion of the nonvolatile write is asyn- chronous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. data# polling (dq 7 ) when the SST39SF020 device is in the internal program operation, any attempt to read dq 7 will produce the complement of the true data. once the program opera- tion is completed, dq 7 will produce true data. the device is then ready for the next operation. during internal erase operation, any attempt to read dq7 will produce a 0. once the internal erase operation is completed, dq7 will produce a 1. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program opera- tion. for sector or chip erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 6 for data# polling timing diagram and figure 15 for a flowchart.
3 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating 0s and 1s, i.e., toggling between 0 and 1. the toggle bit will begin with 1. when the internal program or erase opera- tion is completed, the toggling will stop. the device is then ready for the next operation. the toggle bit is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector or chip erase, the toggle bit is valid after the rising edge of sixth we# (or ce#) pulse. see figure 7 for toggle bit timing diagram and figure 15 for a flowchart. data protection the SST39SF020 device provides both hardware and software features to protect nonvolatile data from inadvert- ent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v cc power up/down detection: the write operation is inhibited when v cc is less than 2.5v. write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit the write operation. this prevents inadvert- ent writes during power-up or power-down. software data protection (sdp) the SST39SF020 provides the jedec approved soft- ware data protection scheme for all data alteration opera- tions, i.e., program and erase. any program operation requires the inclusion of a series of three byte sequence. the three byte-load sequence is used to initiate the pro- gram operation, providing optimal protection from inad- vertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six byte load sequence. the SST39SF020 device is shipped with the software data protection permanently enabled. see table 4 for the specific software command codes. during sdp command sequence, invalid com- mands will abort the device to read mode, within trc. product identification the product identification mode identifies the device as the SST39SF020 and manufacturer as sst. this mode may be accessed by hardware or software operations. the hardware operation is typically used by a programmer to identify the correct algorithm for the SST39SF020 device. users may wish to use the software product identification operation to identify the part (i.e., using the device code) when using multiple manufacturers in the same socket. for details, see table 3 for hardware operation or table 4 for software operation, figure 10 for the software id entry and read timing diagram and figure 16 for the id entry com- mand sequence flowchart. product identification mode exit/reset in order to return to the standard read mode, the software product identification mode must be exited. exiting is accomplished by issuing the exit id command sequence, which returns the device to the read operation. please note that the software reset command is ignored during an internal program or erase operation. see table 4 for software command codes, figure 11 for timing waveform and figure 16 for a flowchart. f unctional b lock d iagram of SST39SF020 t able 1: p roduct i dentification t able address data manufacturers code 0000h bf h device code 0001h b6 h 326 pgm t1.2 y-decoder i/o buffers and data latches 326 ill b1.3 address buffers & latches x-decoder dq 7 - dq 0 a 17 - a 0 oe# ce# we# 2,097,152 bit eeprom cell array control logic
4 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications f igure 1: p in a ssignments for 32- pin tsop p ackages (8mm x 14mm) f igure 2: p in a ssignments for 32- pin pdip s and 32- lead plcc s a11 a9 a8 a13 a14 a17 we# v cc nc a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 326 ill f01.0 standard pinout top view die up 5 6 7 8 9 10 11 12 13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a14 a13 a8 a9 a11 oe# a10 ce# dq7 4 3 2 1 32 31 30 a12 a15 a16 nc v cc we# a17 32-lead plcc top view 32-pin pdip top view 326 ill f02.0 14 15 16 17 18 19 20 dq1 dq2 v ss dq3 dq4 dq5 dq6 nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc we# a17 a14 a13 a8 a9 a11 oe# a10 ce# dq7 dq6 dq5 dq4 dq3
5 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 t able 2: p in d escription symbol pin name functions a 17 -a 0 address inputs to provide memory addresses. during sector erase a 17 -a 12 address lines will select the sector. dq 7 -dq 0 data input/output to output data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. vcc power supply to provide 5-volt supply ( 10%) vss ground nc no connection unconnected pins. 326 pgm t2.1 t able 3: o peration m odes s election mode ce# oe# we# a9 dq address read v il v il v ih a in d out a in program v il v ih v il a in d in a in erase v il v ih v il x x sector address, xxh for chip erase standby v ih x x x high z x write inhibit x v il x x high z/d out x xx v ih x high z/d out x product identification hardware mode v il v il v ih v h manufacturer code (bf) a 17 - a 1 = v il , a 0 = v il device code (b6) a 17 - a 1 = v il , a 0 = v ih software mode v il v il v ih a in id code see table 4 326 pgm t3.4
6 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications t able 4: s oftware c ommand s equence command 1st bus 2nd bus 3rd bus 4th bus 5th bus 6th bus sequence write cycle write cycle write cycle write cycle write cycle write cycle addr (1) data addr (1) data addr (1) data addr (1) data addr (1) data addr (1) data byte program 5555h aah 2aaah 55h 5555h a0h ba (3) data sector erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x (2) 30h chip erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 5555h aah 2aaah 55h 5555h 90h software id exit xxh f0h software id exit 5555h aah 2aaah 55h 5555h f0h notes: (1) address format a 14 -a 0 (hex), addresses a 15, a 16 and a 17 are a dont care for the command sequence. (2) sa x for sector erase; uses a 17 -a 12 address lines (3) ba = program byte address (4) both software id exit operations are equivalent notes for software id entry command sequence 1. with a 17 -a 1 =0; sst manufacturer code = bfh, is read with a 0 = 0, SST39SF020 device code = b6h, is read with a 0 = 1. 2. the device does not remain in software product id mode if powered down. 326 pgm t4.0
7 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 absolute maximum stress ratings (applied conditions greater than those listed under absolute maximum stress ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) temperature under bias ......................................................................................................... ........ -55c to +125c storage temperature ............................................................................................................ .......... -65c to +150c d. c. voltage on any pin to ground potential ............................................................................. -0.5v to v cc + 0.5v transient voltage (<20 ns) on any pin to ground potential ......................................................... -1.0v to v cc + 1.0v voltage on a 9 pin to ground potential ................................................................................................ -0.5v to 14.0v package power dissipation capability (ta = 25c) ............................................................................... ............ 1.0w through hole lead soldering temperature (10 seconds) ........................................................................... ... 300c surface mount lead soldering temperature (3 seconds) ........................................................................... .... 240c output short circuit current (1) ............................................................................................................................... ................................ 100 ma note: (1) outputs shorted for no more than one second. no more than one output shorted at a time. ac c onditions of t est input rise/fall time ......... 10 ns output load ..................... c l = 100 pf for 90 ns output load ..................... c l = 30 pf for 70 ns see figures 12 and 13 o perating r ange range ambient temp v cc commercial 0 c to +70 c 5v10% industrial -40 c to +85 c 5v10%
8 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications t able 6: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read (1) power-up to read operation 100 s t pu-write (1) power-up to write operation 100 s 326 pgm t6.1 t able 7: c apacitance (ta = 25 c, f=1 mhz, other pins open) parameter description test condition maximum c i/o (1) i/o pin capacitance v i/o = 0v 12 pf c in (1) input capacitance v in = 0v 6 pf note: (1) this parameter is measured only for initial qualification and after a design or process change that could affect this parameter . 326 pgm t7.0 t able 8: r eliability c haracteristics symbol parameter minimum specification units test method n end (1) endurance 10,000 cycles mil-std-883, method 1033 t dr (1) data retention 100 years jedec standard a103 v zap_hbm (1) esd susceptibility 1000 volts jedec standard a114 human body model v zap_mm (1) esd susceptibility 200 volts jedec standard a115 machine model i lth (1) latch up 100 + i cc ma jedec standard 78 note: (1) this parameter is measured only for initial qualification and after a design or process change that could affect this parameter . 326 pgm t8.3 t able 5: dc o perating c haracteristics v cc = 5v 10% limits symbol parameter min max units test conditions i cc power supply current ce#=oe#=v il, we#=v ih , all i/os open, read 30 ma address input = v il /v ih , at f=1/t rc min., v cc =v cc max write 50 ma ce#=we#=v il, oe#=v ih, v cc =v cc max. i sb1 standby v cc current 3 ma ce#=v ih, v cc =v cc max. (ttl input) i sb2 standby v cc current 50 a ce#=v cc -0.3v. (cmos input) v cc = v cc max. i li input leakage current 1 a v in =gnd to v cc , v cc = v cc max. i lo output leakage current 1 a v out =gnd to v cc , v cc = v cc max. v il input low voltage 0.8 v v cc = v cc max. v ih input high voltage 2.0 v v cc = v cc max. v ol output low voltage 0.4 v i ol = 2.1 ma, v cc = v cc min. v oh output high voltage 2.4 v i oh = -400a, v cc = v cc min. v h supervoltage for a 9 pin 11.4 12.6 v ce# = oe# =v il , we# = v ih i h supervoltage current 200 a ce# = oe# = v il , we# = v ih , a 9 = v h max. for a 9 pin 326 pgm t5.2
9 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ac characteristics t able 9: r ead c ycle t iming p arameters v cc = 4.5-5.5v SST39SF020-70 SST39SF020-90 symbol parameter min max min max units t rc read cycle time 70 90 ns t ce chip enable access time 70 90 ns t aa address access time 70 90 ns t oe output enable access time 35 45 ns t clz (1) ce# low to active output 0 0 ns t olz (1) oe# low to active output 0 0 ns t chz (1) ce# high to high-z output 15 20 ns t ohz (1) oe# high to high-z output 15 20 ns t oh (1) output hold from address change 0 0 ns 326 pgm t9.2 t able 10: p rogram /e rase c ycle t iming p arameters symbol parameter min max units t bp byte program time 30 s t as address setup time 0 ns t ah address hold time 30 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 0 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph (1) we# pulse width high 30 ns t cph (1) ce# pulse width high 30 ns t ds data setup time 30 ns t dh (1) data hold time 0 ns t ida (1) software id access and exit time 150 ns t se sector erase 10 ms t sce chip erase 20 ms note: (1) this parameter is measured only for initial qualification and after the design or process change that could affect this paramet er. 326 pgm t10.4 note: c l = 100 pf for 90 ns, c l = 30 pf for 70 ns
10 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications f igure 3: r ead c ycle t iming d iagram f igure 4: we# c ontrolled p rogram c ycle t iming d iagram 326 ill f03.0 address a 17-0 dq 7-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz 326 ill f04.3 address a 17-0 dq 7-0 t dh t wph t ds t wp t ah t as t ch t cs ce# sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts byte (addr/data) oe# we# t bp
11 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 f igure 5: ce# c ontrolled p rogram c ycle t iming d iagram f igure 6: d ata # p olling t iming d iagram 326 ill f06.0 address a 17-0 dq 7 dd# d# d we# oe# ce# t oeh t oe t ce t oes 326 ill f05.3 address a 17-0 dq 7-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts byte (addr/data) oe# ce# t bp
12 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications f igure 7: t oggle b it t iming d iagram f igure 8: we# c ontrolled s ector e rase t iming d iagram 326 ill f07.0 address a 17-0 dq 6 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs note: (1) togle bit output is always high first. (1) note: the device also supports ce# controlled sector erase operation. the we# and ce# signals are interchangeable as long as minimum timings are met. (see table 10) sa x = sector address 326 ill f08.4 address a 17-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 30 55 aa 80 aa sa x oe# ce# six-byte code for sector erase t se t wp
13 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 f igure 10: s oftware id e ntry and r ead 326 ill f09.3 address a 14-0 t ida dq 7-0 we# sw0 sw1 sw2 5555 2aaa 5555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa bf b6 55 aa 90 f igure 9: we# c ontrolled c hip e rase t iming d iagram note: the device also supports ce# controlled chip erase operation. the we# and ce# signals are interchangeable as long as minimum timings are met. (see table 10) 326 ill f17.1 address a 17-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 10 55 aa 80 aa 5555 oe# ce# six-byte code for chip erase t sce t wp
14 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications f igure 11: s oftware id e xit and r eset 326 ill f10.0 address a 14-0 dq 7-0 t ida t wp t whp we# sw0 sw1 sw2 5555 2aaa 5555 three-byte sequence for software id exit and reset oe# ce# aa 55 f0
15 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 f igure 12: ac i nput /o utput r eference w aveforms ac test inputs are driven at v iht (2.4 v) for a logic 1 and v ilt (0.4 v) for a logic 0. measurement reference points for inputs and outputs are v ht (2.0 v) and v lt (0.8 v). inputs rise and fall times (10% ? 90%) are <10 ns. f igure 13: a t est l oad e xample 326 ill f12.1 test load example to tester to dut c l r l low r l high v cc note: v ht Cv high test v lt Cv low test v iht Cv input high test v ilt Cv input low test 326 ill f11.1 reference points output input v ht v lt v ht v lt v iht v ilt
16 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications f igure 14: b yte p rogram a lgorithm 326 ill f13.3 start write data: aa address: 5555 write data: 55 address: 2aaa write data: a0 address: 5555 byte address/byte data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed
17 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 f igure 15: w ait o ptions 326 ill f14.4 wait t bp , t sce, or t se program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same byte data# polling write completed write completed read byte is dq 7 = true data? read dq 7 byte program initiated byte program/ sector erase initiated
18 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications f igure 16: s oftware p roduct c ommand f lowcharts 326 ill f15.1 write data: aa address: 5555 software product id entry command sequence write data: 55 address: 2aaa write data: 90 address: 5555 wait t ida read software id write data: aa address: 5555 software product id exit & reset command sequence write data: 55 address: 2aaa write data: f0 address: 5555 write data: f0 address: xx return to normal operation wait t ida wait t ida return to normal operation
19 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 f igure 17: e rase c ommand s equence 326 ill f16.0 write data: aa address: 5555 chip erase command sequence write data: 55 address: 2aaa write data: 80 address: 5555 write data: 55 address: 2aaa write data: 10 address: 5555 write data: aa address: 5555 wait t sce chip erase to ffh write data: aa address: 5555 sector erase command sequence write data: 55 address: 2aaa write data: 80 address: 5555 write data: 55 address: 2aaa write data: 30 address: sa x write data: aa address: 5555 wait t se sector erase to ffh
20 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications device speed suffix1 suffix2 SST39SF020 - xxx - xx - xx package modifier h = 32 leads numeric = die modifier package type p = pdip n = plcc w = tsop (die up) (8mm x 14mm) u = unencapsulated die temperature range c = commercial = 0 to 70c i = industrial = -40 to 85c minimum endurance 4 = 10,000 cycles read access speed 70 = 70 ns, 90 = 90 ns SST39SF020 valid combinations SST39SF020-70-4c-wh SST39SF020-70-4c-nh SST39SF020-70-4c-ph SST39SF020-90-4c-wh SST39SF020-90-4c-nh SST39SF020-90-4c-ph SST39SF020-90-4c-u1 SST39SF020-70-4i-wh SST39SF020-70-4i-nh SST39SF020-90-4i-wh SST39SF020-90-4i-nh example : valid combinations are those products in mass production or will be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combinations.
21 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 packaging diagrams 32-l ead p lastic l ead c hip c arrier (plcc) sst p ackage c ode : nh 32-l ead p lastic d ual - in -l ine p ackage (pdip) sst p ackage c ode : ph 32.pdipph-ill.0 pin 1 index c l 32 1 optional ejector pin indentation shown for conventional mold only base plane seating plane note: 1. complies with jedec publication 95 mo-015 ap dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (min/max). 3. dimensions do not include mold flash. maximum allowable mold flash is .010 inches. .170 .200 7? 4 plcs. .600 bsc .100 bsc .120 .150 .016 .022 .045 .065 .070 .080 .015 .050 .065 .075 1.645 1.655 .008 .012 0? 15? .600 .625 .530 .550 .030 .040 .013 .021 .490 .530 .075 .095 .015 min. .125 .140 top view side view bottom view 1 232 .026 .032 .400 bsc k o r e a 32.plcc.nh-ill.0 note: 1. complies with jedec publication 95 ms-016 ae dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in inches (min/max). 3. dimensions do not include mold flash. maximum allowable mold flash is .008 inches. .050 bsc. .050 bsc. .020 high x .002 deep characters .076/.125 dia. ejector pin 1 .026 .032 .023 .029 .447 .453 .042 .048 .042 .048 .045 dia. x .000/.010 deep polished (optional) .547 .553 .585 .595 .485 .495 .020 r. max. .106 .112 r. x 30?
22 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications 32-l ead t hin s mall o utline p ackage (tsop) sst p ackage c ode : wh 32.tsop-wh-ill.0 note: 1. complies with jedec publication 95 mo-142 ba dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in metric (min/max). 3. coplanarity: 0.1 (.05) mm. 8.10 7.90 .270 .170 1.05 0.95 .50 bsc 0.15 0.05 12.50 12.30 1.10 0.90 pin # 1 ident. dia. 1.00 14.20 13.80 0.70 0.50
23 ? 1998 silicon storage technology, inc. 326-10 12/98 2 megabit multi-purpose flash SST39SF020 preliminary specifications 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 notes:

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